FPGA Implementation Of An LDPC Decoder And Decoding Algorithm Performance
In this work the Low Density Parity Check (LDPC) codes have been introduced and described as very powerful error correcting codes. The whole Thesis has been divided in 5 Chapters: in the first Chapter a generical introduction to Block Codes has been provided, followed by a more deeply description about LDPC codes. In the second Chapter the attention has been posed on the decoding algorithms and decoding architectures that are mostly used in practical cases. Then in the third Chapter a new kind of LDPC decoding architecture has been proposed, while in the fourth Chapter several MATLAB simulations results are shown to explain the behaviour of the different decoding algorithms and their performances. The last Chapter is about the conclusions and eventual improvements to both the presented decoder implementation and to the decoding algorithms used.
SubjectLDPC codes decoding
FPGA implementation of an LDPC decoder
LDPC codes decoding algorithms performance
Date available in INDIGO2013-10-24T20:35:57Z
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