HI PROF : Hardware Interface for Pipelined Reconfiguration of FPGAs
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In recent years FPGAs (Field Programmable Gate Arrays) market has grown dramatically. Increasing of performances and available resources in FPGA devices, due to technological scaling, have led many designers to adopt FPGA-based solution instead of ASIC. Thanks to the fact that FPGAs offer the possibility of reconfiguring hardware, a new concept has born: reconfigurable computing. Reconfigurable computing exploits FPGA to perform tasks by mean of dynamic partial reconfiguration (DPR). DPR allows the task of reconfiguring a articular section of an FPGA design while the remaining part is still running. Reconfigurable computing is becoming increasingly attractive for many applications thanks to its impressive performance and flexibility. However, since development of reconfigurable systems is still a maturing field, there are a number of challenges in developing a reconfigurable system. The goal of this work is to develop a novel hardware infrastructure to implement a high- performance flexible reconfigurable system able to leverage reconfigurable hardware in an efficient way.
dynamic partial reconfiguration